A proposal for data interchange between EDA tools
- Track: EDA devroom
- Room: AW1.121
- Day: Saturday
- Start: 17:00
- End: 17:30
I will present a system for data interchange based on the structural subset of Verilog, extending the usage to express the additional data for layout and schematics. This is an intermediate format to provide a common point for interchange between tools.
More detail is available at http://gnucap.org/dokuwiki/doku.php?id=gnucap:user:netlistimportand_export
The intent is to use this intermediate format to provide convenient data interchange, including bi-directional interchange between incompatible competing tools, for example between Kicad and gEDA. It also eventually should enable things we don't have yet in free EDA, such as post-layout simulation, and schematic vs layout verification.
Speakers
| Al Davis |