Brussels / 1 & 2 February 2020

schedule

RISC-V devroom


09 10 11 12 13 14 15 16 17 18
Saturday How lowRISC made its Ibex RISC-V CPU core faster
Using open source tools to improve an open source core
BlackParrot
An Open Source RISC-V Multicore For and By the World
The HammerBlade RISC-V Manycore
A programmable, scalable RISC-V fabric
Open ESP
The Heterogeneous Open-Source Platform for Developing RISC-V Systems
Building Loosely-coupled RISC-V Accelerators
Using Chisel/FIRRTL to build accelerator templates and collateral for the ESP SoC platform
ERASER: Early-stage Reliability And Security Estimation for RISC-V
An open source framework for resilience/security evaluation and validation in RISC-V processors
RISC-V Software and Firmware Development in the Cloud Using OpenPiton+Ariane on Amazon F1 Cacheable Overlay Manager RISC-V RISC-V Boot flow: What's next ? Oreboot
RISC-V Firmware in Rust
RISC-V Hypervisors
Where are we ? What next ?
Port luajit to RISC-V
Motivation, first steps and perspectives

RISC-V (pronounced "RISC-five") is an open CPU instruction set architecture whose specification is available under the CC-BY license. During the last years, the RISC-V ecosystem has grown tremendously and upstream support for the architecture has been included in significant parts of the free-software landscape (e.g. in binutils, gcc, glibc, qemu and Linux). Multiple Linux distributions are working on ports to the RISC-V architecture and the first commercially available linux-capable RISC-V silicon has been presented at FOSDEM 2018.

The FOSDEM RISC-V devroom covers the current developments in open-source soft- and hardware for the RISC-V architecture.

Event Speakers Start End

Saturday

  How lowRISC made its Ibex RISC-V CPU core faster
Using open source tools to improve an open source core
Greg Chadwick 10:30 10:50
  BlackParrot
An Open Source RISC-V Multicore For and By the World
Dan Petrisko 10:50 11:10
  The HammerBlade RISC-V Manycore
A programmable, scalable RISC-V fabric
Michael Taylor 11:10 11:30
  Open ESP
The Heterogeneous Open-Source Platform for Developing RISC-V Systems
Luca Carloni 11:30 11:50
  Building Loosely-coupled RISC-V Accelerators
Using Chisel/FIRRTL to build accelerator templates and collateral for the ESP SoC platform
Schuyler Eldridge 11:50 12:10
  ERASER: Early-stage Reliability And Security Estimation for RISC-V
An open source framework for resilience/security evaluation and validation in RISC-V processors
Karthik Swaminathan 12:10 12:30
  RISC-V Software and Firmware Development in the Cloud Using OpenPiton+Ariane on Amazon F1 David Wentzlaff 12:30 12:50
  Cacheable Overlay Manager RISC-V Ofer Shinaar 12:50 13:10
  RISC-V Boot flow: What's next ? Atish Patra 13:10 13:30
  Oreboot
RISC-V Firmware in Rust
Ryan O'Leary 13:30 13:50
  RISC-V Hypervisors
Where are we ? What next ?
Anup Patel 13:50 14:10
  Port luajit to RISC-V
Motivation, first steps and perspectives
Anton Kuzmin 14:10 14:30