Brussels / 1 & 2 February 2020


RISC-V devroom

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RISC-V (pronounced "RISC-five") is an open CPU instruction set architecture whose specification is available under the CC-BY license. During the last years, the RISC-V ecosystem has grown tremendously and upstream support for the architecture has been included in significant parts of the free-software landscape (e.g. in binutils, gcc, glibc, qemu and Linux). Multiple Linux distributions are working on ports to the RISC-V architecture and the first commercially available linux-capable RISC-V silicon has been presented at FOSDEM 2018.

The FOSDEM RISC-V devroom covers the current developments in open-source soft- and hardware for the RISC-V architecture.

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