Online / 6 & 7 February 2021

schedule

The Ides of RISC-V

A vectorized Caesar cipher written in RISC-V assembler and tested in an emulator


I will demonstrate how to write a vectorized (parallel) Caesar cipher in RISC-V (in assembler) using the project's emulator. Using the emulator is necessary at this point for such an application because the vectorized extension to the RISC-V ISA is not standardized. I will further demonstrate how the emulator itself is able to emulate the execution of a single user-space application when it is actually designed to emulate an entire system. This will involve a demonstration and explanation of riscv-isa-sim, riscv-pk and their interaction.

Speakers

Will Hawkins

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