FOSDEM 2023
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Schedule
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Events
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Developer rooms
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RISC-V
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QtRVSim—Education from Assembly to Pipeline, Cache Performance, and C Level Programming

QtRVSim—Education from Assembly to Pipeline, Cache Performance, and C Level Programming

Track: RISC-V devroom
Room: K.4.601
Day: Sunday
Start: 09:40
End: 10:20
Video only: k4601
Chat: Join the conversation!

QtRvSim is a graphical RISC-V microprocessor simulator developed to aid computer architecture understanding. It is designed to cover the track of an undergraduate course based on the book "Computer Organization and Design" by Patterson and Hennessy. The class can begin with a single-cycle microarchitecture and gradually add more complex features like pipeline, hazard unit (with or without forward paths), configurable data and instruction cache, emulation of basic system calls, and finally, memory-mapped peripherals. The simulator provides an editor with an integrated assembler. The online version and course materials are available at https://comparch.edu.cvut.cz/.

The simulator is cycle-accurate (memory operations finish within one cycle), compliant with official RISC-V tests, and supports RV32IM, RV64IM (CLI-only), and Zicsr. Featured peripherals are LEDs, knobs with buttons, a terminal, and an LCD display. It is available for Linux, Windows, macOS, and WebAssembly and is developed on GitHub. Many course materials, recordings, and edited lecture videos are also freely available at comparch.edu.cvut.cz. Czech Technical University in Prague, Technical University in Graz, and the University of Colorado at Colorado Springs are currently employing QtRVSim in their classes. Our previous MIPS edition (QtMips) is used by the National and Kapodistrian University of Athens and Charles University in Prague.