As RISC-V reaches maturity, we look at how RISC-V designs are performing. We look at how performance has improved over the years and how performance compares to other cores, particularly those from Arm. We'll explore the impact of different extensions and compilers on performance of compiled code. We'll also look at how useful measuring performance using models is for predicting the performance of real silicon.

Throughout we will use mostly the Embench benchmark suites, with some use of SPEC CPU for application class cores. We will present the first results from the new Embench IoT version 2.0 test suite.

Finally we will show how combining accurate benchmarking with simple machine learning can yield additional performance of compiled software. This will be illustrated with the OpenHW CV32E40Pv2, where we were able to improve benchmarked code density by 7% in just 24 hours.