Currently LLVM saves and restores callee-saved registers during prologue-epilogue insertion pass. I would like to present a new approach where we expose callee-saved register constraints early in the backend pipeline. This creates more opportunities for the optimizers and gives good performance gains. Interestingly, we achieve per-register shrink-wrapping for free. However, this makes emission of CFI directives much more complicated. I am currently in the process of upstreaming this work. The proof-of-concept branch is publicly available here: https://github.com/llvm/llvm-project/pull/90819 I have only tried this approach on RISCV, but it could be applied to other targets as well.