Brussels / 1 & 2 February 2020

schedule

Schuyler Eldridge

I'm a maintainer of the Chisel hardware description language and FIRRTL hardware compiler. I'm also a Research Staff Member at IBM Research.

Links

Events

Title Day Room Track Start End
Building Loosely-coupled RISC-V Accelerators
Using Chisel/FIRRTL to build accelerator templates and collateral for the ESP SoC platform
Saturday K.3.401 RISC-V 11:50 12:10