The use of programmable logic devices, such as FPGAs, requires a range of software tools, from editors for HDL design to the place and route software that maps the design to the physical device and the software that handles the actual configuration process. These are often combined into a coherent IDE to improve efficiency and ease the learning process by offering smooth transitions between the different stages of development, from writing HDL via synthesis, simulation and implementation to the configuration of the device. In the world of FPGAs, these IDEs are mostly proprietary software, developed and owned by the few big FPGA vendors, that only support their own hardware. This means that once design flows are established around one vendor’s software suite, switching to a different vendor’s hardware becomes a tedious or even entirely unworkable task. For years now, pioneers in the open-source community have been steadily working to bridge the gap between commercial and open design tools, to the point that competitive solutions now exist for many aspects of FPGA design. With all the building blocks now available we in the FEntwumS project are now working to integrate a whole range of these tools into one coherent IDE that is as vendor-agnostic as possible and, most importantly, free and open-source. As a representative case study to validate and benchmark this platform, we integrate OpenEye, an open-source and fully FPGA-compatible neural network accelerator developed within the consortium. Its scalable architecture enables us to evaluate the robustness of the toolchain across different device classes and design configurations, testing synthesis behavior, implementation quality and runtime characteristics. By using OpenEye as a practical test vehicle, we ensure transparent evaluation, reproducibility and alignment with the open-source philosophy that underpins the entire project. In this talk, we will present our approach, our current progress, issues we have encountered and our future plans.