RISC-V had 40 years of history to learn from: What it gets right, and what it gets hilariously wrong
- Track: RISC-V
- Room: H.2214
- Day: Saturday
- Start: 11:20
- End: 11:55
- Video only: h2214
- Chat: Join the conversation!
A discussion of historical lessons that RISC-V did learn from, and mistakes that it repeated. Focused on the design constraints forced by RVC and RVV, as well as the choices around breaking out the F and D profiles out from a mandatory vector unit, and the state changes that come with it.
The broad context will be specific to OoO SS processors
Speakers
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FelixCLC |