Danfeng Zhang
NPU architect and performance engineer with deep experience in RISC-V, heterogeneous acceleration, and low-level optimization. Designed instruction sets, built high-performance compute kernels, and optimized algorithms across CPUs, GPUs, and custom NPUs. Now studying at the University of Warsaw while continuing to push hardware and software to their limits.
Events
| Title | Day | Room | Track | Start | End |
|---|---|---|---|---|---|
| All in RISC-V, RISC-V All in AI: Solving Real AI Compute Challenges with DeepComputing & Tenstorrent |
Saturday | UD2.120 (Chavanne) | AI Plumbers | 17:50 | 18:10 |